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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004, 2003, zarlink semiconductor inc. all rights reserved. features ? meets requirements of telcordia gr-253-core for sonet stratum 3 clocks ? meets requirements of telcordia gr-1244-core for stratum 3 clocks ? meets requirements of g.813 option 1 and 2 for sdh equipment clocks (sec) ? 8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz input reference frequencies ? output clock frequencies from 8 khz to 155.52 mhz ? low intrinsic jitter and wander generation ? selectable operation modes ? alarm output indication applications ? sonet/sdh add/drop multiplexers ? sonet/sdh up-links ? atm edge switches ? line cards december 2003 ordering information ZL30461MGG 240 bga 0 c to +70 c zl30461 compact stratum 3 timing module data sheet figure 1 - functional block diagram
zl30461 data sheet 2 zarlink semiconductor inc. description the zl30461 is a compact timing module, which functi ons as a complete system clock solution for general stratum 3 and sonet/sdh timing applications. the zl30461 uses zarlink's digital and analog phase locked loop (dpll and apll) technology and can lock to 1 of 4 input frequencies automatically. the module has multip le output clocks ranging from 8 khz to 155.52 mhz, its primary output at 77.76 mhz has low jitter performance at less than 40 ps (pk to pk). the availability of multiple clocks and features such as holdover and out-of-range detection enable the zl30461 to be used on the master timing card as well as the linecard. figure 2 - 240 pin bga top view note: all undefined pins must be left unconnected. pin description ball # bga name description m1 pri primary reference (input) . this input is a primary reference source for synchronization. the module can synchr onize to falling edge of the following reference clocks: 8 khz, 1. 544 mhz, 2.048 mhz or the rising edge of 19.44 mhz. this pin is selected when a logic 0 is applied to the refsel input pin. this pin is internally pulled to v dd1 . t a b c d e f g h u j k l m n p r 1 2 3 4 5 6 7 8 9 1011121314151617
zl30461 data sheet 3 zarlink semiconductor inc. l1 sec secondary reference (input) . this input is a secondary reference source for synchronization. the module can synchr onize to falling edge of the following reference clocks: 8 khz, 1. 544 mhz, 2.048 mhz or the rising edge of 19.44 mhz. this pin is selected when a logic 1 is applied to the refsel input pin. this pin is internally pulled to v dd1 . a10 prior primary reference rejection range (output) . when used in stratum 3 applications, a logic 1 at this output pin indicates that the primary reference is off the pll centre frequency by more than 1 2 ppm. this threshold is relative to the accuracy of the 20 mhz mast er oscillator input osci. b10 secor secondary reference rejection range (output) . when used in stratum 3 applications, a logic 1 at this output pin indicates that the primary reference is off the pll centre frequency by more than 1 2 ppm. this threshold is relative to the accuracy of the 20 mhz mast er oscillator input osci. b15 refsel reference source select (input) . logic 0 selects the pri (primary) reference source as the input reference signal and logic 1 selects the sec (secondary) input. the logic level at this input is sampled on the rising edge of f8o. this pin is internally pulled to gnd. a8 reset reset (5 v tolerant input) . logic 0 will forces the module into a reset state. this pin must be held to logic 0 for a minimum of 1 s to reset the module properly. the module must be re set after power-up. a11 lock lock indicator (output) . logic 1 at this output indicates that the clock synthesizer outputs are locked to the selected input reference. logic 0 indicates that the selected input reference has exceeded (or is close to) the core pll frequency tracking range. this threshold is set at 1 04 ppm and is relative to the accuracy of the 20 mhz master oscillator input osci. a12 holdover holdover indicator (output) . logic 1 at this output indicates that the module is in holdover. b16 refalign reference align (input) . a high to low transition at this input initiates phase realignment between the input reference and the generated output clocks. this pin is internally pulled to gnd. j1 ms1 mode select 1 (input) . the ms1 and ms2 inputs select the module?s mode of operation (normal, holdover or free-run), see table 1 for details. the logic level at this input is sampled on the rising edge of the f8o frame pulse. k1 ms2 mode select 2 (input) . the ms2 and ms1 inputs select the module?s mode of operation (normal, holdover or free-run), see table 1 for details. the logic level at this input is sampled on the rising edge of the f8o frame pulse. a9 oe output enable (input) . logic 1 on this input enables c19o, f16o , c16o , c8o, c6o, c4o , c2o, c1.5o, f8o and f0o signals. logic 0 will forc e these output clocks pins into a high impedance state. u8 ja19oe ja19mo output enable (input) . logic 1 on this input will enable the ja19mo output clock and logic 0 will disable this it. (note 1) u10 ja77oe ja77p/n output enable (input) . logic 1 on this input will enable the ja77p/n output clock and logic 0 will disable this it. (note 1) u5 ja19mo ja 19.44 mhz clock (output) . this output provides a low jitter 19.44 mhz clock. pin description (continued) ball # bga name description
zl30461 data sheet 4 zarlink semiconductor inc. k17 j17 ja77p ja77n ja 77.76 mhz clock (lvpecl output) . this differential output provides a low jitter 77.76 mhz clock. g2 f0o frame pulse st-bus 2.048 mbps (output) . this is an 8 khz, 244 ns, active low framing pulse, which marks the beginning of a st-bus frame. this is typically used for st-bus operation at 2.048 mbps and 4.096 mbps. h2 f8o frame pulse st-bus/gci 8.192 mbps (output) . this is an 8 khz, 122 ns, active low framing pulse, which marks the beginni ng of a st-bus/gci frame. this is typically used for st-bus/gci operation at 8.192 mbps. e2 f16o frame pulse st-bus 8.192 mbps (output) . this is an 8 khz, 61 ns, active low framing pulse, which marks the beginning of a st-bus frame. this is typically used for st-bus operation at 8.192 mbps. d17 c1.5o clock 1.544 mhz (output) . this output provides a 1.544 mhz ds1 rate clock. g1 c2o clock 2.048 mhz (output) . this output provides a 2.048 mhz e1 rate clock, which can be used for st-bus operation at 2.048 mbps. f2 c4o clock 4.096 mhz (output) . this clock is used for st-bus operation at 4.096 mbps. d16 c6o clock 6.312 mhz (output) . this output provides a 6.312 mhz ds2 rate clock. f1 c8o clock 8.192 mhz (output) . this clock is used for st-bus operation at 8.192 mbps. e1 c16o clock 16.384 mhz (output) . this clock is used for st-bus operation at 16.384 mbps. t11 c19o clock 19.44 mhz (output) . this output provides a 19.44 mhz clock, which must be connected to the refin input. t10 refin apll reference (input) . this is the input reference of the apll circuitry and must be linked directly to the c19o output. (note 1) b17 c34-c44 clock 34.368 mhz / clock 44.736 mhz (output) . this clock can provide several frequency outputs, depending on the status of the e3/ds3 and e3ds3/oc3 input pins, see figure 4 for details. r1 p1 c155p c155n clock 155.52 mhz (lvds output) . differential outputs for a 155.52 mhz clock. these outputs are enabled by applying logic 0 to e3ds3/oc3 input or can be switched into high impedance state by applying logic 1 to e3ds3/oc3 input. k2 e3ds3/oc3 e3ds3 or oc3 selection input . logic 0 on this pin enables the c155p/n outputs and enables the c34/c44 output to prov ide an 8.592 mhz or 11.184 mhz clock. logic 1 at this input sets the c155p/n clock outputs into high impedance and enables c34/c44 outputs to provide 34.368 mhz or 44.736 mhz clock. l2 e3/ds3 e3 or ds3 selection (input) . when the e3ds3/oc3 pin is set to logic 1, a logic 0 on e3/ds3 pin selects a 44.736 mhz clock on c34/c44 output and logic 1 selects 34.368 mhz clock. when the e3ds3/oc3 pin is set to logic 0, a logic 0 on e3/ds3 pin selects 11.184 mhz clock on c34/c44 output and logic 1 selects 8.592 mhz clock. pin description (continued) ball # bga name description
zl30461 data sheet 5 zarlink semiconductor inc. d1 fcs filter selector (input) . logic 0 on this pin sets th e filter corner frequency to 1.5 hz, this selection meets requirements of g.813 option 1 and gr-1244 stratum 3 clocks. logic 1 on this pin sets the filter corner frequency to 0.1 hz, this selection meets requirements of g.813 option 2, gr-253 for sonet stratum 3 and gr-253 for sonet minimum clocks (smc). a16 osco oscillator out (output) . this output provides ac cess to the internal 20 mhz tcxo and will normally be co nnected to the osci pin. a15 osci oscillator in (input) . this is the master 20 mhz clock input pin and is normally connected directly to the osco (internal txco) pin. however, this input can be connected to an external 20 mhz reference if required. if an external reference is going to be used, then the tv dd , tgnd and osco pins should be left unconnected; this will save on power and reduce any unwanted noise. a13, b13 tv dd tcxo positive power supply a14, b14, c13, c14, d10 - d15, e10 - e13 tgnd tcxo ground t14, u14 v cc positive power supply. note 1. h1, j2, v dd1 positive power supply k4, k5, l4, l5, m4, m5, v dd2 positive power supply. note 1. j3, k3 av dd positive power supply f16, f17 v cc v co positive power supply. note 1. n15, p15, t16, u16 v cpecl positive power supply. note 1. h4, h5, j4, j5 agnd1 ground g13 - g16, h13 - h16, j13 - j16, k13 - k16, l13 - l16, m13 - m16, n8 - n14, n16, p8 - p14, p16, r8 - r16, t12, t13, t15, u12, u13, u15, u17 agnd2 ground pin description (continued) ball # bga name description
zl30461 data sheet 6 zarlink semiconductor inc. c3 - c8, d3 - d9, e3 - e9, f3 - f5, g3 - g5, h3, n1 - n7, p2 - p7, r2, r3, t1, t2 dgnd ground b12, t6, t8, t9, u6, u7, u9, u11,t5 gc ground connections (input). internal gates to be exte rnally connected to dgnd. b7 hw hardware/software control (input). if this input is tied to logic 0, then the module is controlled via the microprocessor port. if it is tied to logic 1, then the module is controlled via the control pins ms1, ms2, fcs, refsel, /refalign, e3/ds3 and e3ds3/oc3. b8 cs chip select (5 v tolerant input). this active low input enables the microprocessor interface. when this input is at logic 1, the microprocessor interface is idle and all data bus i/o pins will be in a high impedance state. b9 ds data strobe (5 v tolerant input). this input is the active low data strobe of the processor interface. a7 r/w read/write strobe (5 v tolerant input). this input controls the direction of the data bus i/o during a microprocessor acce ss. when the r/w input is logic 1, the processor is reading data from the stat e control machine. when logic 0, the processor is writing to the state control machine. a2 a0 address 0 (5 v tolerant input). address input for the microprocessor interface. a0 is the least significant input. a1 a1 address 1 (5 v tolerant input). address input a1 for the microprocessor interface. b2 a2 address 2 (5 v tolerant input). address input a2 for the microprocessor interface. b1 a3 address 3 (5 v tolerant input). address input a3 for the microprocessor interface. c2 a4 address 4 (5 v tolerant input). address input a4 for the microprocessor interface. c1 a5 address 5 (5 v tolerant input). address input a5 for the microprocessor interface. d2 a6 address 6 (5 v tolerant input). address input a6 for the microprocessor interface. a6 is the most significant input a6 d0 data 0 (5 v tolerant three-state i/o). data input/output fo r the microprocessor port, d0 is the least significant bit. b6 d1 data 1 (5 v tolerant three-state i/o). data input/output for the microprocessor port (d0 - d7). a5 d2 data 2 (5 v tolerant three-state i/o). data input/output for the microprocessor port (d0 - d7). b5 d3 data 3 (5 v tolerant three-state i/o). data input/output for the microprocessor port (d0 - d7). pin description (continued) ball # bga name description
zl30461 data sheet 7 zarlink semiconductor inc. note 1: connections relate to the analog pll stage, if the ji tter attenuated outputs are not being used, you do not need to make these connections. a4 d4 data 4 (5 v tolerant three-state i/o). data input/output for the microprocessor port (d0 - d7). b4 d5 data 5 (5 v tolerant three-state i/o). data input/output for the microprocessor port (d0 - d7). a3 d6 data 6 (5 v tolerant three-state i/o). data input/output for the microprocessor port (d0 - d7). b3 d7 data 7 (5 v tolerant three-state i/o). data input/output for the microprocessor port (d0 - d7), d7 is the most significant bit. u4 tdo ieee1149.1a test data output. jtag serial data is output on this pin on the falling edge of tclk clock. if not used, this pin should be left unconnected. u3 tms ieee1149.1a test mode se lection (3.3 v input). jtag signal that controls the state transition on the tap controller. this pin is internally pulled to v dd . if not used, this pin should be left unconnected. u1 tclk ieee1149.1a test clock signal (3.3 v input). input clock for the jtag test logic. if not used, this pin should be pulled up to v dd . u2 trst ieee1149.1a reset si gnal (3.3 v input). asynchronous reset for the jtag tap controller. this pin should be pulsed low on power-up to ensure that the tap is reset. this pin is internally pulled down to dgnd. if not used, this pin should be left unconnected. e16,e17, f15,g17, h17,l17, m17,n17, p17,r17, t17, nc do not connect to these pins, internal connections t3 tdi ieee1149.1a test data input (3.3 v input). input for jtag serial test instructions and data. this pin is internally pulled up to v dd1 . if not used, this pin should be left unconnected. pin description (continued) ball # bga name description
zl30461 data sheet table of contents 8 zarlink semiconductor inc. 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 acquisition plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 core pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 digitally controlled oscillator (dco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.1 filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.2 lock indicator (lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.3 reference alignment (refalign). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.1 clock synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.2 jitter attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.3 clock formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.4 output clocks phase adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5 control state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.1 clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.2 zl30461 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.2.1 reset state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.2.2 free-run state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.2.3 normal state (locked state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.2.4 holdover state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.2.5 auto holdover state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.3 state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.6 tcxo and master clock frequency calibration circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.7 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.8 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.0 hardware and software contro l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 hardware co ntrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1.2 status pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 software control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.1 control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.2 status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.3 zl30461 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.4 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1 zl30461 mode switching - examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.1 system start-up sequence: free-run --> holdover --> normal . . . . . . . . . . . . . . . . . . . . 31 3.1.2 single reference operation: normal --> auto ho ldover --> normal . . . . . . . . . . . . . . . . 31 3.1.3 dual reference operation: normal --> auto holdover --> holdover --> normal . . . . 32 3.1.4 reference switching (refsel): no rmal --> holdover --> normal . . . . . . . . . . . . . . . . . . . . 33 3.2 master/slave timing protection switchin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3 programming mast er clock oscillator frequency calibration register . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.0 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
zl30461 data sheet list of figures 9 zarlink semiconductor inc. figure 1 - functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - 240 pin bga top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3 - lvpecl output termination circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4 - c155o and c34/c44 clock generation options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5 - zl30461 state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6 - hardware and software control options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7 - transition from free-run to normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8 - automatic entry into auto holdover state and recovery into normal mode . . . . . . . . . . . . . . . . . . . . . 32 figure 9 - entry into auto holdover state and recovery in to normal mode by switching references . . . . . . . . . 33 figure 10 - manual reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11 - block diagram of the master/slave timing protecti on switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12 - timing parameters measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13 - microport timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14 - st-bus and gci output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 15 - ds1, ds2 and c19o clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 16 - c155o and c19o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 17 - input reference to output clock phase alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 18 - input control signal setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 19 - e3 and ds3 output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
zl30461 data sheet list of tables 10 zarlink semiconductor inc. table 1 - loop filter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2 - operating modes and states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3 - filter characteristic selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4 - reference source select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5 - zl30461 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6 - control register 1 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7 - status register 1 (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8 - control register 2 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9 - phase offset register 2 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10 - phase offset register 1 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11 - device id register (r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12 - control register 3 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13 - clock disable register 1 (r/w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14 - clock disable register 2 (r/w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15 - core pll control register (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16 - fine phase offset register (r/w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17 - primary acquisition pll status register (r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18 - secondary acquisition pll status register (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19 - master clock frequency calibration register 4 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 20 - master clock frequency calibration register 3 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 21 - master clock frequency calibration register 2 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 22 - master clock frequency calibration register 1 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
zl30461 data sheet 11 zarlink semiconductor inc. 1.0 functional description the zl30461 offers a complete timing solution in a bga module package. the zl30461 has been designed to provide timing for sdh and sonet equi pment, conforming to itu-t, ansi, etsi and telcordia recommendations. in addition, it generates clocks for legacy pdh equipment operating at ds1, ds2, e1 and e3 rates. the zl30461 also provides clocks for industry standard st-bus an d gci backplanes. the functional block diagram for the module is shown in figure 1 ?functio nal block diagram? and its operation is described in the following sections. 1.1 acquisition plls the zl30461 has two acqu isition plls for monitoring availability and quality of t he primary (pri) and secondary (sec) reference clocks. each acquisiti on pll operates independently and locks to the falling edges of input reference frequencies: 8 khz, 1.544 mhz, 2.048 mhz or to the rising edge of 19.44 mhz. the reference frequency can be determined from reading the acquisition pll status register bits inpfreq1 and inpfreq0 (see table 17 ?primary acquisition pll status register (r)? and tabl e 18 ?secondary acquisition pll status register (r)?). the primary and secondary acquisition plls are designed to provide status information that identifies three levels of reference clock quality. for clarity, only the primary acquisition pll is referenced in the text, but the same applies to the secondary acquisition pll. ? reference frequency drifts more than 30000 ppm or is lost completely. in response, the primary acquisition pll enters its own holdover state and indicates this by asserting the holdover bit in the primary acquisition pll status register (tabl e 17 ?primary acquisition pll status register (r)?). entry into holdover forces the core pll into the auto holdover state. ? reference frequency drifts more than 104 ppm. in response, the primary acquisition pll asserts the frequency limit bit pafl in its primary acquisition p ll status register (table 17), indicating that the reference frequency crossed the boundary of the capture range. ? reference frequency drifts more than 12 ppm. in response, the prior (primary reference acceptance range) bit and pin change state to logic 1, in confo rmance with stratum 3 requirements defined in gr-1244- core. outputs of both acquisition plls are connected to a mu ltiplexer (mux), which allows selecting a reference signal that guarantees better tracea bility to the primary reference clock. this multiplexer channels bi nary words to the core pll digital phase detector (instead of analog signals). the digital phase detector in the core pll eliminates quantization errors and improves phase alignment accuracy. the bandwidth of the acquisition pll is much wider than the bandwidth of the following core pll. this feature allows cascading acquisition and core plls without changing the transfer function of the core pll. 1.2 core pll the most critical element of the zl30461 is the core pl l. this generates a phase-locked clock, filters jitter and wander and suppresses input phase transients. all of thes e features are in agreement with international standards: ? g.813 option 1 clocks for sdh equipment ? gr-253 for sonet stratum 3 and sonet minimum clocks (smc) ? gr-1244 for stratum 3 clocks the core pll supports three mandatory modes of operat ion: free-run, normal (locked) and holdover. each of these modes places specific requirements on the building blocks of the core pll. ? in free-run mode, the core pll locks to the 20 mhz master clock oscillator connected to pin osci. the stability of the generated clock remains the same as the stability of the master clock oscillator but frequency accuracy can be greatly improved by use of the master clock frequency calibration register. this register compensates oscillator frequency, practica lly eliminating manufacturing tolerances.
zl30461 data sheet 12 zarlink semiconductor inc. ? in normal mode, the core pll locks to one of t he acquisition plls. both acquisition plls provide preprocessed phase data to the core pll including detec tion of reference clock quality. this preprocessing reduces the load on the core pll and improves quality of the generated clock. ? in holdover mode, the core pll generates a clock based on data collected from past reference signals. the core pll enters holdover mode if the attached acqui sition pll switches into the holdover state under external software or hardware control. 1.3 digitally controlled oscillator (dco) the dco is an arithmetic unit that continuously generat es a stream of numbers representing the phase-locked clock. these numbers are passed to the clock synthesi zer (see section 1.4) wher e they are converted into electrical clock signals of different frequencies. 1.3.1 filters in normal mode, the clock generated by the dco is phase-locked to the input reference signal and band-limited to meet network synchronization standards. the zl30461 prov ides four software programmable (fcs bit in control reg 1 and fcs2 bit in control reg 3) and two hardware selectable (fcs pin) filt ering options. the filtering characteristics are similar to a first order low pass filter with corner frequencies that support international standards: 1.3.2 lock indicator (lock) the zl30461 is considered locked (lock = 1) when the residual phase movement after declaring locked condition does not exceed 20 ns; as required by standard wander gener ation mtie and tdev tests. to ensure the integrity of the lock status indication, the zl30461 holds lock bit/ pin low for a minimum of 65 sec in the 0.1 hz filtering mode and 10 sec in the 1.5 hz filtering mode. 1.3.3 reference alignment (refalign ) when the zl30461 finishes locking to a reference an arbi trary phase difference will remain between its output clocks and its reference; this phase difference is part of the normal operation of the zl30461. if so desired, the output clocks can be brought into ph ase alignment with the pll reference (see figure 17) by using the refalign control bit/pin. using refalign with 1.544 mhz, 2.048 mhz or 19.44 mhz reference if the zl30461 is locked to a 1.544 mhz, 2.048 mhz or 19. 44 mhz reference, then the output clocks can be brought into phase alignment with the pll reference by using the refalign control bit/pin according to one of the procedures below: fcs2 (bit) fcs (pin/bit) filter conformance 001.5hz meets requirements of g.813 option 1 and gr-1244 stratum 3, stratum 4e and stratum 4 clocks.the maximum phase slope is limited to 41 ns in 1.326 ms. 010.1hz meets requirements of g.813 option 2 and gr-253 for sonet stratum 3. the maximum phase slope is limited to 885 ns in one second. 1 0 12 hz this filter config uration limits output phase slope to 1200 s/sec. 116hz meets requirements of g.813 option 1 for sdh equipment clocks (sec) and gr-1244 for stratum 4 and stratum 4e clocks. the maximum phase slope is limited to 50 ns in 1.326 ms. table 1 - loop filter selection
zl30461 data sheet 13 zarlink semiconductor inc. for 0.1 hz filtering applications (fcs=1, fcs2=0) ? wait until the zl30461 lock indicator is high, indicating that it is locked ? pull fcs low ? pull refalign low ? hold refalign low for 250 s ? pull refalign high ? wait until the lock indicator goes high ? pull fcs high after initiating a reference realignment, the zl30461 will ent er holdover mode for 200 ns while aligning the internal clocks to remove the static phase error. the zl30461 will th en begin the normal locki ng procedur e. the lock indicator will go low 5 sec after refalign is pulled low and it will remain low for 10 sec. for 1.5 hz filtering applications (fcs=0, fcs2=0) ? wait until the zl30461 lock indicator is high, indicating that it is locked ? pull refalign low ? hold refalign low for 250 s ? pull refalign high after initiating a reference realignment the z l30461 will enter holdover mode for 200 ns while aligning the internal clocks to remove the static phase error. the zl30461 will th en begin the normal locki ng procedur e. the lock indicator will go low 5 sec after refalign is pulled low and it will remain low for 10 sec. for 6 hz and 12 hz filtering applications (fcs=1, fcs2=1 or fcs=0, fcs2=1) ? wait until the zl30461 lock indicator is high, indicating that it is locked ? pull refalign low ? hold refalign low for 250 s ? pull refalign high after initiating a reference realignment the z l30461 will enter holdover mode for 200 ns while aligning the internal clocks to remove the static phase error. the zl30461 will then begin the normal locking procedure. the lock pin will remain high during t he realignment process. using refalign with an 8 khz reference if the zl30461 is locked to an 8 khz reference, then the ou tput clocks can be brought into phase alignment with the pll reference by using the refalign control bit/pin according to one of the procedures below: for 0.1 hz filtering applications (fcs=1, fcs2=0) ? wait until the zl30461 lock indicator is high, indicating that it is locked ? pull fcs low ? pull refalign low ? hold refalign low for 10 sec ? pull refalign high ? wait until the lock indicator goes high ? pull fcs high
zl30461 data sheet 14 zarlink semiconductor inc. after initiating a reference realignment the z l30461 will enter holdover mode for 200 ns while aligning the internal clocks to remove the static phase error. the zl30461 will then begin the normal locking procedure. the lock pin will remain high during t he realignment process. for 1.5 hz filtering applications (fcs=0, fcs2=0) ? wait until the zl30461 lock indicator is high, indicating that it is locked ? pull refalign low ? hold refalign low for 10 sec ? pull refalign high after initiating a reference realignment the z l30461 will enter holdover mode for 200 ns while aligning the internal clocks to remove the static phase error. the zl30461 will then begin the normal locking procedure. the lock pin will remain high during t he realignment process. for 6 hz and 12 hz filtering applications (fcs=1, fcs2=1 or fcs=0, fcs2=1) ? wait until the zl30461 lock indicator is high, indicating that it is locked ? pull refalign low ? hold refalign low for 3 sec ? pull refalign high after initiating a reference realignment the z l30461 will enter holdover mode for 200 ns while aligning the internal clocks to remove the static phase error. the zl30461 will then begin the normal locking procedure. the lock pin will remain high during t he realignment process. 1.4 output clocks the zl30461 has multiple clock outputs, from the clock synthersizer and the jitter attenuator. the very low jitter output clocks of the 19.44 mhz and 77.76 mhz are used for the backplane clocks and the high speed optical framers and physical interfaces 1.4.1 clock synthesizer the output of the core pll is connect ed to the clock synthesizer that g enerates 12 clocks and three frame pulses. 1.4.2 jitter attenuator the zl30461 output driver circuit provides a jitter at tenuated output at 77.76 mhz with less than 40 ps jitter performance. this output must be terminated co rrectly and failure to do so will af fect the modules performance. the recommend termination for this output is shown in figure 3. in addition to the 77.76 mhz outp ut, the zl30461 also provides a 19.44 mhz jitter attenuated output.
zl30461 data sheet 15 zarlink semiconductor inc. figure 3 - lvpecl output termination circuit 1.4.3 clock formats the zl30461 outputs the following clock and frame pulses: ? c1.5o: 1.544 mhz clock with nominal 50% duty cycle ? c2o: 2.048 mhz clock with nominal 50% duty cycle ?c4o : 4.096 mhz clock with nominal 50% duty cycle ? c6o: 6.132 mhz clock with nominal 50% duty cycle ? c8o: 8.192 mhz clock with nominal 50% duty cycle ? c8.5o: 8.592 mhz clock with duty cycle from 30% to 70% ? c11o: 11.184 mhz clock with duty cycle from 30% to 70% ? c16o : 16.384 mhz clock with nominal 50% duty cycle ? c19o: 19.44 mhz clock with nominal 50% duty cycle ? c34o: 34.368 mhz clock with nominal 50% duty cycle ? c44o: 44.736 mhz clock with nominal 50% duty cycle ? c155p/n: 155.52 mhz clock with nominal 50% duty cycle ? ja19mo: 19.44 mhz clock with nominal 50% duty cycle ? ja77p/n: 77.76 mhz clock with nominal 50% duty cycle ?f0o : 8 khz frequency, with 244 ns wide, logic low frame pulse ? f8o: 8 khz frequency, with 122 ns wide, logic high frame pulse ? f16o : 8 khz frequency, with 61 ns wide, logic low frame pulse the combination of two pins, e3ds3/oc3 and e3ds3, controls the selection of different clock configurations (see figure 4 ?c155o and c34/c44 clock generation options? for details). lvpecl driver lvpecl receiver = 50? = 50? vcc note : vcc = +3.3v 127? 127? 82.5? 82.5? zl30461 output driver
zl30461 data sheet 16 zarlink semiconductor inc. figure 4 - c155o and c34/c44 clock generation options 1.4.4 output clocks phase adjustment the zl30461 provides three control registers dedicated to programming the output clock phase offset. clocks c16o , c8o, c4o , c2o and frame pulses f16o , f8o and f0o are derived from 16.384 mhz and can be jointly shifted with respect to an active reference clock by up to 125 s with a step size of 61 ns. the required phase shift of clocks is programmable by writing to the phase offset register 2 (table 9) and to the phase offset register 1 (table 10). the c1.5o clock can be shif ted as well in step sizes of 81ns by programming c1.5poa bits in control register 3 (table 12). the coarse phase adjustment is augment ed with a very fine phase offset cont rol of approximately 477 ps per step. this fine adjustment is programmable by writing to the fine phase offset register (table 16 ?fine phase offset register (r/w)?). the offset moves all clocks and frame pulses generated by zl30461 including c155 clock. 1.5 control state machine 1.5.1 clock modes any network element that operates in a synchronous ne twork must support three clock modes: free-run, normal (locked) and holdover. these clock modes determine th e behavior of a network element to the unforeseen changes in the network synchronization hierarchy. requirements for clock modes are defined in the international standards e.g.: g.812, g.813, gr-1244-core and gr-253-c ore and they are very strictly enforced by network operators. the zl30461 supports all clock modes and eac h of these modes have a corresponding state in the control state machine. 1.5.2 zl30461 state machine the zl30461 control state machine is a complex combin ation of many internal states supporting the three mandatory clock modes. the simplified version of this st ate machine is shown in figure 5 and it includes the mandatory states: free-run, normal and holdover. these three states are complemented by two additional states: reset and auto holdover, which are critical to the zl30461 operation under the changing external conditions. 155.52 hiz 11.184 44.736 8.592 34.368 ____ e3ds3/oc3 ____ e3ds3/oc3 11 1 00 0 e3/ds3 c155 output c34/44 output
zl30461 data sheet 17 zarlink semiconductor inc. figure 5 - zl30461 state machine 1.5.2.1 reset state the reset state must be entered when zl30461 is powered-up. in this state, all arithmet ic calculations are halted, clocks are stopped, the microprocessor port is disabled and all internal registers are reset to their default values. the reset state is enter ed by pulling the reset pin to logic 0 for a minimum of 1 s. when the reset pin is pulled back to logic 1, internal logic starts a 625 s in itialization process before swit ching into the free-run state (ms2, ms1 = 10). it is recommended to perform a module reset immediately after power up, to ensure the zl30461 is set to a know state. 1.5.2.2 free-run state the free-run state is entered when synchronization to the ne twork is not required or is not possible. typically, this occurs during installation, repairs or when a network element operates as a master node in an isolated network. in the free-run state, the accu racy of the generated clocks is determined by the accuracy and stability of the zl30461 master crystal oscillator. when equipmen t is installed for the first time (or pe riodically maintained ), the accuracy of the free-run clocks can be adjusted to within 1x10 -12 by setting the offset frequency in the master clock frequency calibration register. when powering up the equipment, it is recommended that the module has at least 12 hours to stabilize after the equipm ent has reached it norma l operating temperature. 1.5.2.3 normal state (locked state) the normal state is entered when normal mode is select ed and a good quality reference clock is available. the zl30461 automatically detects the frequency of the refe rence clock (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) and sets the lock status bit and pin to logic 1 after acquiring synchronization. in the normal state all generated clocks (c1.5o, c2o, c4o , c6o, c8o, c16o , c19o, ja19mo, c34/c44, ja77 and c155) and frame pulses (f0o , f8o, f16o ) are derived from network timing. to guarantee un interrupted synchronization, the zl30461 has two normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or refsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 _____ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual} notes: 0 --> 1 : transition from 0 to 1 &= : and operation != : not equal == : equal {auto} : automatic transition auto holdover: automatic holdover state ms2, ms1 {manual} : manual transition {ahrd} : automatic holdover {mhr} : manual holdover
zl30461 data sheet 18 zarlink semiconductor inc. acquisition plls that contin uously monitor the quality of the incoming reference clocks. this dual architecture enables quick replacement of a poor or failed refere nce and minimizes the time spent in other states. during this state the zl30461 can tolerate a frequency ch ange (on the active input) without generating an alarm or changing state. with the 0.1 hz filter selected, the m odule can withstand a 0.06 ppm change and with the 1.5 hz filter selected, the module can withstand a 10 ppm change. 1.5.2.4 holdover state the holdover state is typically entered for short durations while network synchronizatio n is temporarily disrupted. in holdover mode, the zl30461 generated clocks are not locked to an external reference signal, but these outputs are based on stored coefficients in memory. these coefficients are determined while the module is in normal state for at least 10 minutes after th e modules stabilization period. the initial frequency offset of the zl30461 ?s core pll in holdover mode is 32x10 -12 . this is more accurate than telcordia?s gr-1244-core stratum 3e requirement of 1x10 -9 . once the zl30461 has transitioned into holdover mode, holdover stability is de termined by the stability of the 20 mhz ma ster clock oscillator applied to the osci pin. the on-board tcxo conforms to telcordia? s gr-1244-core stratum 3 requirement of 50x10 -9 , with a short term stability of 0.37x10 -6 , for the first 24 hours (after th e module?s stab ilization period). 1.5.2.5 auto holdover state the auto holdover state is a transitional state that the zl30461 enters automatically when the active reference fails unexpectedly. when the zl30461 detects loss of referenc e, it sets the holdover status bit and waits in auto holdover state until the failed reference recovers. the hold over status may alert the control processor about the failure and in response the control proc essor may switch to the secondary re ference clock. the auto holdover and holdover states are internally combined together and they are output as a holdover status pin and bit 4 in status register 1 (table 7). 1.5.3 state transitions in a typical network element application, the zl3046 1 will typically operate in normal mode (ms2, ms1 == 00) generating synchronous clocks. its two acquisition plls will continuous ly monitor the input references for signs of degraded quality and output status information for further processing. the status information from the acquisition plls and the core pll, combined with status information from line interfaces and framers (as listed below), forms the basis for creating reliable network synchronization. ? acquisition plls (prior, se cor, pah, pafl, sah, safl) ? core pll (lock, holdover, flim) ? line interfaces (e.g. los - loss of signal, ais - alarm indication signal) ? framers (e.g. lof - loss of frame or synchronizati on status messages carried over sonet s1 byte or esf-ds1 facility data link) the zl30461 state machine is designed to perform some transitions automatically, leaving other less time dependent tasks to the control processor. the state mach ine includes two stimulus signals which are critical to automatic operation: ?ok --> fail? and ?fail --> ok? that represent loss (and recovery) of reference signal or its drift by more than 30000 ppm. both of them force the core pll to transition into and out of the auto holdover state. the zl30461 state machine may also be driven by controlling the mode select pins or bits ms2, ms1. in order to avoid network synchronization problems, the state machine has built-in basic protection that does not allow switching the core pll into a state where it cannot operate correctly e.g. it is not possible to force the core pll into normal mode when all references are lost.
zl30461 data sheet 19 zarlink semiconductor inc. 1.6 tcxo and master clock frequency calibration circuit in an ordinary timing generation module, the free-run mo de accuracy of generated cloc ks is determined by the accuracy of the master crystal oscillator. if the master crystal oscillator has a manuf acturing tolerance of +/- 4.6 ppm, the generated clocks will have no better accuracy. the zl30461 has its own on-board stratum 3 tcxo (+/-4.6 ppm), which outputs 20 mhz on the osco pin. for most applications this oscillator offe rs sufficient accuracy and can be conn ected back into the module by simply linking the osco in osci pins together. however, if a mo re accurate reference is required, then the on-board tcxo can be disconnected completely and an external 20 mhz reference applied to the osci pin. if any external reference is going to be used, then it is recommended that the tcxo power applied to the tv dd and tgnd pins is removed. this will minimize the risk of noise or harmonics causing any problems. the zl30461 minimizes tolerance problems by providin g a programmable master clock frequency calibration circuit. this can reduce the oscillato r manufacturing tolerance to near zero. the feature reduces th e need for high precision 20 mhz crystal oscilla tors, that could be very expensive, for eq uipment that has to maintain accuracy over a very long period of time (e.g. 20 years in some applications). the compensation value for the master clock calibration register (mcfc3 to mcfc0) can be calculated from the following equation: mcfc = 45036 * f offset where: f offset = f m - 20 000 000 hz (eq 1) the f m frequency should only be measured after the master oscillator has been powe red long enough for it to reach a steady operating temperature. the zl30461 should have a warm-up time of 10 hours to ensure that the module has reached a stable operating temperature ( however, reasonable operation can be expected with 30 minutes). section 3.3 provides two examples of how to calculate an offset frequency and convert the decimal value to a binary format. the maximum frequency compensation r ange of the mcfc register is equal to 2384 ppm (47680 hz). 1.7 microprocessor interface the zl30461 dpll can be controlled by a device connected di rectly to the hardware control pins. if the hw pin is tied to logic 0 (see figure 6 ?hardware and software control options?), a microprocessor with a motorola type bus may be used to control pll operation and check its stat us. under software control, the control pins ms2, ms1, fcs, refsel, refalign are disabled and they are replaced by the equivalent control bits. the output pins lock, holdover, prior and secor are always active and provid e current status information whether the device is in microprocessor or hardware control. software (microprocesso r) control provides additional functionality that is not available in hardware control such as output clock phase adjustment, master clock frequency calibration and extended access to status registers. 1.8 jtag interface the zl30461 core pll jtag (joint test action group) interface conforms to the boundary-scan standard ieee1149.1-1990, th at specifies a design- for-testability technique called b oundary-scan test (bst). the bst architecture is made up of four basic elements, test access port (tap), t ap controller, instru ction register (ir) and test data registers (tdr), and all these elements are implemented on the zl30461. zarlink semiconductor provides a boundary scan descrip tion language (bsdl) file that contains all the information required for a jtag test system to access t he zl30461's core pll boundary scan circuitry. the file is available for download from the zarlink semiconductor web site: www.zarlink.com.
zl30461 data sheet 20 zarlink semiconductor inc. 2.0 hardware and software control the zl30461 offers hardware and software control options that simplify design of basic or complex clock synchronization modules. hardwa re control offers fewer feat ures but still allows for build ing of sophisticated timing cards without extensive programming. the complete set of control and status functions for each mode are shown in figure 6 ?hardware and software control options?. figure 6 - hardware and software control options 2.1 hardware control the hardware control is a su bset of software control an d it will only be briefly desc ribed with cross- referencing to software control programmable registers. s t a t u s c o n t r o l hw = 1 hardware control software control ms2 ms1 bga balls fcs refsel _______ refalign lock holdover prior secor c o n t r o l s t a t u s ms2 ms1 fcs refsel _______ refalign ahrd mhr flim pah pafl sah safl hw = 0 p lock holdover prior secor
zl30461 data sheet 21 zarlink semiconductor inc. 2.1.1 control pins the zl30461 has six dedicated control pins for selecting modes of operation and acti vating different functions. these pins are listed below: ms2 and ms1 pins: mode select. the ms2 and ms1 inputs select the pll mode of operation. see table 2 for details. the logic level at these inputs is samp led by the rising edge of the f8o frame pulse. fcs pin: filter characteristic select. the fcs input is used to select the f iltering characteristic s of the core pll. see table 3 for details. refsel: reference source select. the refsel input selects the pri (primary) or sec (secondary) input as the reference clock for the core pll. the logic level at this input is sampled by the rising edge of f8o. refalign : reference align. the refalign input controls phase realignment between the input reference and the generated output clocks. ms2 ms1 mode of operation 0 0 normal mode 0 1 holdover mode 1 0 freerun mode 11reserved table 2 - operating modes and states fcs filtering characteristic phase slope 0 filter corner frequency set to 1.5 hz. this selection meets requirements of g.813 option 1 and gr-1244 stratum 3 clocks. 41 ns in 1.326 ms 1 filter corner frequency set to 0.1 hz. this selection meets requirements of g.813 option 2, gr-253 for sonet stratum 3 and gr-253 for sonet minimum clocks (smc). 885 ns/s table 3 - filter characteristic selection refsel input reference 0 core pll connected to the primary acquisition pll 1 core pll connected to the secondary acquisition pll table 4 - reference source select
zl30461 data sheet 22 zarlink semiconductor inc. 2.1.2 status pins the zl30461 has four dedicated status pins for indica ting modes of operation and quality of the primary and secondary reference clocks. these pins are listed below: lock - this output goes to logic 1 when the core pll is locked to the selected acquisition pll. holdover - this output goes to l ogic 1 when the core pll enters holdov er mode. the core pll will switch to holdover mode if the respective acquisition pll enters hold over mode or if the mode select pins or bits are set to holdover (ms2, ms1 = 01). prior - primary reference acceptance range. this output goes to logic 1 when the primary reference frequency is outside of the acquisition pll 12 ppm acceptance range. secor - secondary reference acceptance range. this output goes to logic 1 when the secondary reference frequency is outside of the acquisition pll 12 ppm acceptance range. 2.2 software control software control is enabled by setting the hw pin to logi c 0 (hw = 0). in this mode all hardware control pins (inputs) are disabled, but the status (outputs) are still enab led. the zl30461 has 18 regi sters that provide all the functionality available in hard ware control and also offer advanced contro l and monitoring that is only available in software control (see figure 6 ?hardware and software control options?). 2.2.1 control bits the zl30461 has seven control bits as is shown in figu re 6 ?hardware and software control options?. five bits replace the five hardware control pins: ms2, ms1, fcs, refsel and refalign (table5: control register 1), and two bits support recovery from auto holdover mode: ahrd and mhr (table 15: core pll control register). in addition to the control bits shown in figure 6 ?hardware and software control options?, the zl30461 has a number of bits and registers that are accessed infre quently or during configuration only e.g. phase offset adjustment or master clock frequency calibration. 2.2.2 status bits the zl30461 has nine status bits (see figure 6 ?hardwar e and software control options?, tables 6, 17 and 18). four bits perform the same function as their equivalent status pins (p rior, secor, lock and holdover). five bits perform two functions. bits flim, pafl, safl indicate drift of the reference clock frequencies beyond the capture range of acquisition and core plls and bits pah and sah show entry of primary and secondary acquisition plls into holdover mode. these bits are desc ribed in detail in section 2.2.3. the status pins are enabled when the zl30461 operates in software control and they can be used to trigger interrupts. 2.2.3 zl30461 register map addresses: 00h to 6fh address hex register read write function 00 control register 1 r/w refsel, 0, 0, ms2, ms1, fcs, 0, refalign 01 status register 1 r prior, secor, lo ck, holdover, rsv, flim, rsv, rsv table 5 - zl30461 register map
zl30461 data sheet 23 zarlink semiconductor inc. note: the zl30461 uses address space from 00 h to 6 fh. registers at address locations not listed above must not be written or re ad. 2.2.4 register description address: 00 h 04 control register 2 r/w e3ds3/oc3 , e3/ds3 , 0, 0, 0, 0, 0, 0, 06 phase offset register 2 r/w 0, 0, 0, 0, offen, c16poa10, c16poa9, c16poa8 07 phase offset register 1 r/w c16poa7, c16poa6, c16poa5, c16poa4, c16poa3, c16poa2, c16poa1, c16poa0 0f device id register r 0111 0000 11 control register 3 r/w rsv, rsv, c1.5 poa2, c1.5poa1, c1.5 poa0, 0, 0, fcs2 13 clock disable register 1 r/w 0, 0, c16od is, c8odis, c4odis, c2odis, c1.5odis,0 14 clock disable register 2 r/w 0, 0, 0, f 8odis, f0odis, f16odis, c6odis, c19odis 19 core pll control register r/w 0, 0, 0, 0, 0, mhr, ahrd, 0 1a fine phase offset register r/w fpoa7, fpoa6, fpoa5, fpoa4, fpoa3, fpoa2, fpoa1, fpoa0 20 primary acquisition pll status register r rsv, rsv, rsv, inpfreq1, inpfreq0, rsv, pah,pafl 28 secondary acquisition pll status register r rsv, rsv, rsv, inpfreq1, inpfreq0, rsv, sah, safl 40 master clock frequency calibration register - byte 4 r/w mcfc31, mcfc30, mcfc29, mcfc28, mcfc27, mcfc26, mcfc25, mcfc24, 41 master clock frequency calibration register - byte 3 r/w mcfc23, mcfc22, mcfc21, mcfc20, mcfc19, mcfc18, mcfc17, mcfc16 42 master clock frequency calibration register - byte 2 r/w mcfc15, mcfc14, mcfc13, mcfc12, mcfc11, mcfc10, mcfc9, mcfc8 43 master clock frequency calibration register - byte 1 r/w mcfc7, mcfc6, mcfc5, mcfc4, mcfc3, mcfc2, mcfc1, mcfc0 bit name functional description default 7refsel reference select. a zero selects the pri (primary) reference source as the input reference signal and a one selects the sec (secondary) reference. 0 6-5 rsv reserved. 00 table 6 - control register 1 (r/w) address hex register read write function table 5 - zl30461 register map (continued)
zl30461 data sheet 24 zarlink semiconductor inc. address: 01 h 4-3 ms2, ms1 mode select. - ms2 = 0 ms1 = 0 normal mode (locked mode) - ms2 = 0 ms1 = 1 holdover mode - ms2 = 1 ms1 = 0 free-run mode - ms2 = 1 ms1 = 1 reserved 10 2fcs filter characteristic select. (see table 12 for complimentary fcs2 bit description) - fcs2 = 0, fcs = 0: filter corner frequency set to 1.5 hz - fcs2 = 0, fcs = 1: filter corner frequency set to 0.1 hz - fcs2 = 1, fcs = 0: filter corner frequency set to 12 hz - fcs2 = 1, fcs = 1: filter corner frequency set to 6 hz conformance of these filter settings to standards is presented in table 1. 0 1rsv reserved. 0 0 refalign reference align. a high-to-low transition aligns the generated output clocks to the input reference signal (see section 1.3.3 for details). this bit should never be held low permanently. 1 bit name functional description 7prior primary reference acceptance range. a one indicates that the primary reference is off the nominal frequency by more than 12 ppm. this indicator has built-in hysteresis and is updated once a second. monitoring is a lways active and is independent of filter characteristics (fcs). switch ing thresholds are determined by the accuracy of the master clock osci. in an ex treme case when over time the master clock oscillator drifts 4.6 ppm, the switchi ng thresholds will drift as well. the master clock frequency calibration register can be used to eliminate dependence of prior (secor) switching threshold a nd free-run mode accuracy on the master crystal oscillator tolerance. 6secor secondary reference acceptance range. a one indicates that the secondary reference is off the nominal frequency by more than 12 ppm. functionally, this bit is equivalent to the prior bit for primary acquisition pll. 5 truelock true lock. this bit goes to 1 when the core p ll is locked to the selected acquisition pll (142 ppm - relative to the accuracy of the 20 mhz master oscillator input osci). 4holdover holdover. this bit goes to 1 when the core pll is in holdover mode. 3rsv reserved. 2flim frequency limit. this bit goes to 1 when the core pll is pulled by the input reference signal to the edge of its frequency tracking range set at 104 ppm (relative to the accuracy of the 20 mhz master oscillator input osci). this bit may change state momentarily in the event of large jitter or wander excursions occurring when the input reference is close to the frequency limit range. table 7 - status register 1 (r) bit name functional description default table 6 - control register 1 (r/w) (continued)
zl30461 data sheet 25 zarlink semiconductor inc. address: 04 h address: 06 h 1rsv reserved. 0rsv reserved. bit name functional description default 7e3ds3/oc3 e3, ds3 or oc-3 clock select. setting this to 0 enables the c155p/n outputs and enables the c34/c44 output to provide c8 or c11 clocks. a 1 sets the c155 clock outputs into high impedance and enables the c34/c44 output to provide a c34 or c44 clock. 0 6e3/ds3 e3 or ds3 clock select. when e3ds3/oc3 bit is 1, a 0 on the e3/ds3 bit selects a 44.736 mhz clock on the c34/c44 output and a 1 selects a 34.368 mhz clock. when the e3ds3/oc3 bit is set to 0, a 0 on the e3/ds3 bit selects an 11.184 mhz clock on the c34/c44 output and a 1 selects an 8.592 mhz clock. 0 5-0 rsv reserved. 000000 table 8 - control register 2 (r/w) bit name functional description default 7-4 rsv reserved. 0000 3offen offset enable. set to 1 to enable programmable phase offset adjustment (c16 phase offset adjustment and c1 .5 phase offset adjustment) between the input reference and the generated clocks. 0 2-0 c16poa10 to c16poa8 c16 phase offset adjustment. these three bits (most significant) in conjunction with the eight bits of phas e offset register 1 allow for phase shifting of all clocks and frame puls es that are derived from the c16 clock (c8o, c4o , c2o, f16o , f8o, f0o). the phase offset is an unsigned number in a range from 0 to 2047. each increment by one represents phase-offset advancement by 61.035 ns with respect to the input reference signal. the phase offset is a two-byte value and it must be written in one step increments. for example: from a current position of 22h, four writes are required to advance the clocks by 244 ns: write 23h, 24h, 25h, 26h. writing numbers in reverse order will delay clocks from their present position. 000 table 9 - phase offset register 2 (r/w) bit name functional description table 7 - status register 1 (r) (continued)
zl30461 data sheet 26 zarlink semiconductor inc. address: 07 h address: 0f h address: 11 h bit name functional description default 7-0 c16poa7 to c16poa0 c16 phase offset adjustment. the eight least significant bits of the phase offset adjustment word. see the ph ase offset register 2 for details. 0000 0000 table 10 - phase offset register 1 (r/w) bit name functional description 7-4 id7 - 4 device identification number. these four bits represent the device part number. the id number for zl30461 is 0111. 3-0 id3 - 0 device revision number. these bits represent the revision number, starts from 0000. table 11 - device id register (r) bit name functional description default 7rsv reserved. 0 6rsv reserved. 0 5-3 c1.5poa2 to c1.5poa0 c1.5 phase offset adjustment. these three bits allow for changing of the phase offset of the c1.5o clock relative to the active input reference. the phase offset is an unsigned number in a range from 0 to 7. each increment by one represents phase-offset advancement by 80.96 ns. example: writing 010 advances the c1.5o clock by 162 ns, writ ing 001 delays this clock by 80.96 ns from this (010) position, writing 000 will remove programmed the offset. 000 2-1 rsv reserved. 000 0fcs2 filter characteristic select. (see table 6 for complimentary fcs bit description) - fcs2 = 0, fcs = 0: filter corner frequency set to 1.5 hz. - fcs2 = 0, fcs = 1: filter corner frequency set to 0.1 hz. - fcs2 = 1, fcs = 0: filter corner frequency set to 12 hz. - fcs2 = 1, fcs = 1: filter corner frequency set to 6 hz. conformance of these filter settings to standards is presented in table 1. 000 table 12 - control register 3 (r/w)
zl30461 data sheet 27 zarlink semiconductor inc. address: 13 h address: 14 h bit name functional description default 7-6 rsv reserved. 00 5 c16odis c16o (16.384 mhz) clock disable. when set to 1, this bit tristates the 16.384 mhz clock output. 0 4 c8odis c8o (8.192 mhz) clock disable. when set to 1, this bit tristates the 8.192 mhz clock output. 0 3 c4odis c4o (4.096 mhz) clock disable. when set to 1, this bit tristates the 4.096 mhz clock output. 0 2c2dis c2o (2.048 mhz) clock disable. when set to 1, this bit tristates the 2.048 mhz clock output. 0 1 c1.5dis c1.5o (1.544 mhz) clock disable. when set to 1, this bit tristates the 1.544 mhz clock output. 0 0rsv reserved. 0 table 13 - clock disable register 1 (r/w) bit name functional description default 7-5 rsv reserved. 000 4 f8odis f8o frame pulse disable. when set to 1, this bit tristates the 8 khz 244 ns active high framing pulse output. 0 3 f0odis f0o frame pulse disable. when set to 1, this bit tristates the 8 khz 122 ns active low framing pulse output. 0 2 f16odis f16o frame pulse disable. when set to 1, this bit tristates the 8 khz 61 ns active low framing pulse output. 0 1 c6odis c6o (6.312 mhz) clock disable. when set to 1, this bit tristates the 6.312 mhz clock output. 0 0 c19odis c19o (19.44 mhz) clock disable. when set to 1, this bit tristates the 19.44 mhz clock output. 0 table 14 - clock disable register 2 (r/w)
zl30461 data sheet 28 zarlink semiconductor inc. address: 19 h address: 1a h bit name functional description default 7-3 rsv reserved. 00000 2mhr manual holdover release . a change form 0 to 1 on the mhr bit will release the core pll from auto holdover when automatic return from holdover is disabled (ahrd is set to 1). this bit is level sensitive and it must be cleared immediately after it is set to 1 (next writ e operation). this bit has no effect if ahrd is set to 0. 0 1ahrd automatic holdover return disable . when set high, this bit inhibits the core pll from automatically switching back to normal mode from auto holdover state when the active acquisition pll regains lock to input reference. the active acquisition pll is the acquisition pll to which the core pll is currently connected. 0 0rsv reserved. 0 table 15 - core pll control register (r/w) bit name functional description default 7-0 fpoa7 - 0 fine phase offset adjustment. this register allows phase offset adjustment of all output clocks and frame pulses (c16o , c8o, c4o , c2o, f16o , f8o, f0o , c155o, c19o, ja19mo, c34/44, ja77p/ n) relative to the active input reference. the adjustment can be positi ve (advance) or negative (delay) with a nominal step size of 477 ps (61.035 ns / 128). the rate of phase change is limited to 885 ns/s in sonet stratum 3, and 41ns in 1.326 ms for all other filter characteristic se lections. the phase offset value is a signed 2?s complement number e.g.: advance: +1 step = 01h, +2 st eps = 02h, +127 steps = efh delay: -1 step = ffh, -2 steps = feh, -128 steps = 80h example: writing 08h advances all cl ocks by 3.8 ns and writing f3h delays all clocks 0000 0000 table 16 - fine phase offset register (r/w)
zl30461 data sheet 29 zarlink semiconductor inc. address: 20 h address: 28 h bit name functional description 7-5 rsv reserved. 4-3 inpfreq1-0 input frequency. these two bits identify the primary reference clock frequency. - 00 = 19.44 mhz - 01 = 8 khz - 10 = 1.544 mhz - 11 = 2.048 mhz 2rsv reserved. 1pah primary acquisition pll holdover. this bit goes to 1 whenever the acquisition pll enters holdover mode. holdover mode is entered when the reference frequency: - is lost completely - drifts more than 30000 ppm off from the nominal frequency - of a large phase hit occurs on the reference clock 0pafl primary acquisition pll frequency limit. this bit goes to 1 whenever the acquisition pll exceeds its capture range of 104 ppm. this bit can flicker high in the event of a large excursion of still tolerabl e input jitter. table 17 - primary acquisition pll status register (r) bit name functional description 7-5 rsv reserved. 4-3 inpfreq1-0 input frequency. these two bits identify the secondary reference clock frequency. - 00 = 19.44 mhz - 01 = 8 khz - 10 = 1.544 mhz - 11 = 2.048 mhz 2rsv reserved. 1sah secondary acquisition pll holdover. this bit goes to 1 whenever the acquisition pll enters holdover mode. holdover mode is entered when the reference frequency: - is lost completely - drifts more than 30000 ppm off from the nominal frequency - of a large phase hit occurs on the reference clock 0 safl secondary acquisition pll frequency limit. this bit goes to 1 whenever the acquisition pll exceeds its capture range of 104 ppm. this bit can flicker high in the event of a large excursion of still tolerabl e input jitter. table 18 - secondary acquisition pll status register (r)
zl30461 data sheet 30 zarlink semiconductor inc. address: 40 h address: 41 h address: 42 h address: 43 h 3.0 applications this section contains applic ation specific details for mo de switching, master clock o scillator calibration and power supply decoupling for the analog pll. 3.1 zl30461 mode switching - examples the zl30461 is designed to transition from one mode to the other driven by the internal state machine or by manual control. the following examples present a couple of typical scenarios of how the zl30461 can be employed in network synchronization equipment (e.g. timing modules, line cards or stand alone synchronizers). bit name functional description default 7-0 mcfc32-24 master clock frequency calibration. this most significant byte contains the 31st to 24th bit of the master clock frequency calibration register. see applications section 3. 3 for a detailed description of how to calculate the mcfc value. 0000 0000 table 19 - master clock frequency calibration register 4 (r/w) bit name functional description default 7-0 mcfc23-16 master clock frequency calibration. this byte contains the 23rd to 16th bit of the master clock frequency calibration register. 0000 0000 table 20 - master clock frequency calibration register 3 (r/w) bit name functional description default 7-0 mcfc15-8 master clock frequency calibration. this byte contains the 15th to 8th bit of the master clock frequency calibration register. 0000 0000 table 21 - master clock frequency calibration register 2 (r/w) bit name functional description default 7-0 mcfc7-0 master clock frequency calibration. this byte contains bit 7 to bit 0 of the master clock frequency calibration register. 0000 0000 table 22 - master clock frequency calibration register 1 (r/w)
zl30461 data sheet 31 zarlink semiconductor inc. 3.1.1 system star t-up sequence: free-run -- > holdover --> normal the free-run to holdover to normal transition represents a sequence of steps that will most likely occur during a new system installation or scheduled ma intenance of timi ng cards. the process starts from the reset state and then transitions to free-run state when the device is bei ng initialized. at the end of this process, the zl30461 should be switched into normal mode (with ms2, ms1 set to 00) instead of holdover mode. if the reference clock is available, the zl30461 will tr ansition briefly into holdover state to acquire synchroniz ation and switch automatically to normal state. if the reference clock is not available, the zl304 61 will stay in holdover state indefinitely. whilst in holdover state, the core pll will cont inue generating clocks with the same a ccuracy as in th e free-run mode, waiting for a valid reference clock. when the system is connected to the networ k (or timing card switched to a valid reference), the acquisition pll will quickl y synchronize and clear its own holdov er status (pah bit). this will enable the core pll to start the syn chronization process. after acquiring lock , the zl30461 will automatically switch from holdover state to normal stat e without system intervention. th is transition to the normal state will be flagged by the lock status bit and pin. figure 7 - transition from free-run to normal mode 3.1.2 single reference operation: normal --> auto holdover --> normal the normal to auto-holdover to norm al transition will usually happen when the network element loses its single reference clock unexpectedly or when it has two referenc es but switching to the secondary reference is not a desirable option. the sequence starts with the unexpected failure of a refer ence signal shown as transition ok --> fail in figure 8 ?automatic entry into auto holdover state and recovery into normal mode? at a time when zl30461 operates in normal mode. this failure is detected by the active acquisition pll based on th e following fail criteria: ? frequency offset on 8 khz, 1.544 mhz, 2.048 mhz and 19.44 mhz reference clocks exceeds 30000 ppm (3%). ? phase hit on 1.544 mhz, 2.048 mhz and 19.44 mhz exceeds half of the cycle of the reference clock. normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or refsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 _____ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual}
zl30461 data sheet 32 zarlink semiconductor inc. after detecting any of these anomalies on a refe rence clock the acquisition pll will s witch itself into holdover state forcing the core pll to automatically s witch into the auto holdov er state. this condition is flagged by lock = 0 and holdover = 1. figure 8 - automatic entry into auto holdover state and recovery into normal mode there are two possible returns to normal mode after the reference signal is restored: ? with the ahrd (automatic holdover return disable) bit set to 0. in this case, the core pll will automatically return to the normal state after the refe rence signal recovers from failure. this transition is shown on the state diagram as a fail --> ok change. this change becomes effective when the reference is restored and there have been no phase hits detected for at least 64 clock cycles. ? with the ahrd bit set to 1 to disable automatic return to normal state and the change of mhr (manual holdover release) bit from 0 to 1 to trigger the transiti on from auto holdover to normal state. this option is provided to protect the core pll from toggling betw een normal and auto holdover states in case of an intermittent quality reference. in the case w hen mhr has been changed when the reference is still not available (acquisition pll in holdover state), the transition to normal state will not occur and mhr 0 to 1 transition must be repeated. this transition from auto holdover to normal state is performed as ?hitless? reference switching. 3.1.3 dual reference operation: normal --> auto holdover --> holdover --> normal the normal to auto-holdover to holdover to normal sequ ence represents the most likely operation of zl30461 in network equipment. the sequence starts from the normal state and transitions to auto holdover state due to an unforeseen loss of reference. the failure conditions triggering this transi tion were described in sectio n 3.1.2. when in the auto holdover state, the zl30461 can return to normal state automatically if the lost reference is restored and the adhr bit is set to 0. if the reference clock failure persists fo r a period of time that exce eds the system design limit, the system control processor may initiate a reference switch. if the secondary reference is available the zl30461 will briefly switch into holdover state and then transition to normal state. normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or refsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 _____ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual} automatic return to normal: ahdr=0 or manual return to normal: ahrd=1 & mhr 0--> 1
zl30461 data sheet 33 zarlink semiconductor inc. figure 9 - entry into auto holdover state and recovery into normal mode by switching references the new reference clock will most likely have a different phas e, but it may also have a different fractional frequency offset. to lock to a new reference wit h a different frequency, the core pl l will step gradually towards the new frequency. the frequency slope will be limited to less than 2.0 ppm/sec. 3.1.4 reference switching (refse l): normal --> holdover --> normal the normal to holdover to normal sequenc e switching is usually performed when: ? a reference clock is available but its frequency drifts beyond some specified limit. in a network element with stratum 3 internal clocks, the reference failure is declared when its frequency drifts more than 12 ppm beyond its nominal frequency. the zl30461 indicates this condition by setting prior or secor status bits and pins to logic 1. ? during routine maintenance of equipment orderly switch ing of reference clocks is possible. this may occur when synchronization references must be rearrange d or when a faulty line card must be replaced. normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or refsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 _____ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual} ahrd=0 (automatic return enabled)
zl30461 data sheet 34 zarlink semiconductor inc. figure 10 - manual reference switching two types of transitions are possible: ? semi-automatic transition, which involves changing refsel input to select a secondary reference clock without changing the mode select inputs ms2, ms1 = 00 (normal mode). this forces zl30461 to momentarily transition through the holdover state and automatically return to normal state after synchronizing to a secondary reference clock. ? manual transition, which involves switching into hol dover mode (ms2, ms1 = 01), changing references with refsel, and manual return to the normal mode (ms2, ms1 = 00). in both cases, the change of refe rences provides ?hitless? switching. 3.2 master/slave timing protection switching carrier-class telecommunications equipment deployed in today?s networks guarantee better than 99.999% operational availability (equivalent to less th an 7 minutes of downtime per year). this high level of uninterrupted service is achieved by fully redundant architectures wit h hot swappable cards. timing for these types of systems can be generated by the zl30461, which supports master/s lave timing protection switching, shown in figure 11. the redundant architecture shown in this figure is bas ed on the zl30461 being deployed on two separate timing cards; the master timing card and the slave timing card . in normal operation, the master timing card receives synchronization from the network and provides timing for the whole system. all line cards in the system are configured to receive from the backplane a reference cl ock generated by the master timing card. the redundant slave timing card is phase locked (through the sec input) to one of the backplane clocks supplied by the master timing card. the zl30461 on the slave timing card is programmed for 12 hz loop filter operation (fcs2=1, fcs=0) which allows it to tr ack the master timing card clocks with minimal phase error. when the master timing card fails unexpectedly, (this failure is not related to reference failure), then all line cards will detect this failure and they will switch to the timing supplied by the slave timing card. at this moment the zl30461 on the slave timing card must be switched from 12 hz to the same loop filter characteristic (e.g. 1.5 hz filter for sdh networks) as the master timing card. normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or refsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 _____ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual}
zl30461 data sheet 35 zarlink semiconductor inc. figure 11 - block diagram of the ma ster/slave timing protection switching a detailed description of this master/slave redundant timing architecture based on zl30461 can be found in application note zlan-67 ?applications of the zl30461 master/slave application?. 3.3 programming master clock oscillator frequency calibration register the master crystal oscillator and its programmable master clock frequency calibration register (see table 19, table 20, table 21, and table 22) have been descri bed in section 1.6 ?tcxo and master clock frequency calibration circuit?. programming of this register should be done after system has been powered long enough for the master crystal oscillator to reach a steady operating te mperature. when th e temperature stabilizes the crystal oscillator frequency should be measur ed with an accurate freq uency meter. the frequency measur ement should be substituted for the f offset variable in the following equation. mcfc = 45036 * f offset (eq 2) where f offset is the crystal oscillator frequen cy offset from the nomi nal 20 000 000 hz freque ncy expressed in hz. example 1: calculate the binary value that mu st be written to the mcfc register to correct a +1 ppm offset of the master crystal oscillator. the +1 ppm offset fo r a 20 mhz frequency is equivalent to 20 hz: mcfc = 45036 * 20 = 900720 = 00 0d be 70 h (eq 3) example 2: calculate the binary value that must be written to th e mcfc register to correct a -2 ppm offset of the master crystal oscillator. the -2 ppm offset for 20 mhz frequency is equivalent to -40 hz: mcfc = 45036 * (-40) = -1801440 = ff e4 83 20 h (eq 4) timing card (active master) zl30461 pri sec r0 r1 timing card (active slave) zl30461 pri sec r0 r1 linecard #n zl30461 sonet/sdh framers linecard #n zl30461 e3/ds3 mux with framers backplane pri pri sec sec
zl30461 data sheet 36 zarlink semiconductor inc. 4.0 characteristics 4.1 ac and dc electrical characteristics absolute maxi mum ratings* * voltages are with respect to ground (gnd) unless otherwise stated. * exceeding these values may cause permanent damage. functi onal operation under these conditions is not implied. recommended operating conditions* * voltages are with respect to ground (gnd) unless otherwise stated. parameter symbol min. max. units 1 supply voltages v dd av dd tv dd -0.3 5.0 v 2 input voltage v in -0.05 v dd +0.5 v parameter symbol min. typ. max. units 1 supply voltages v dd av dd tv dd 3.135 3.3 3.465 v 2 operating temperature t a 025 70 o c dc electrical characteristics* characteristics symbol min. typ. max. units test conditions 1 supply current i dd 450 ma output unloaded 2 supply current ti dd 20 ma output unloaded 3 high-level input voltage v ih 0.7v dd v 4 low-level input voltage v il 0.3v dd v 5 input leakage current i il 15 a v i =v dd or gnd 6 high-level output voltage v oh 2.4 v i oh = 8 ma 7 low-level output voltage v ol 0.4 v i ol = 8 ma 8 lvds: differential output voltage v od 250 450 mv z t =100 ohms 9 lvds: change in vod between complementary output states dv od 50 mv z t =100 ohms 10 lvds: offset voltage v os 1.125 1.375 v note 1 11 lvds: output short circuit current i os 24 ma pin short to gnd
zl30461 data sheet 37 zarlink semiconductor inc. * voltages are with respect to ground (gnd) unless otherwise stated. note 1: vos is defined as (v oh + v ol ) / 2. note 2: rise and fall times are measured at 20% and 80% levels. 12 lvds: output rise and fall times t rf 260 900 ps note 2 13 lvpecl: differential output voltage |v od | 480 600 720 mv z t =100 ohms 14 lvpecl: high-level output voltage v oh v dd -0.9 v z t =100 ohms 15 lvpecl: low-level output voltage v ol v dd -1.5 v 16 lvpecl: output rise and fall times t rf 200 ps note 2 ac electrical characteristics* parameter symbol min. max. units test conditions 1 i/p frequency range f in hz note 3 2 o/p frequency range f out hz note 4 3 reference rejection r rej gr-1244 3.5: r3-36 g.813 6.3a 4 reference pull-in r pull gr-1244 3.5: r3-37 gr-253 5.4.4.2.3: r5- 126 g.813 6.1a,b 5 reference hold-in r hold gr-1244 3.5: r3-38 gr-253 5.4.4.2.3: r5- 126 g.813 6.2b 6 reference settling time r stime gr-1244 3.5: r3-39 gr-253 5.4.4.2.3: r5- 128 7 jitter tolerance j t gr-1244 4.2: r4-2, cr4-3, r4-4 gr-253 5.6.2.2: r5- 240, r5-241 g.813 8.2a,b 8 wander tolerance w tol gr-1244 4.3: r4-5 gr-253 5.4.4.2.4: r5- 129 g.813 8.1 a,b 9 phase transient tolerance p tt gr-1244 4.4: r4-7 gr-253 5.4.4.3.3: r5- 135 dc electrical characteristics* (continued) characteristics symbol min. typ. max. units test conditions
zl30461 data sheet 38 zarlink semiconductor inc. * voltages are with respect to ground (gnd) unless otherwise stated. note 3: 8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz. note 4: various outputs from 8 khz to 155.52 mhz. note 5: with reference to the free-run accuracy. 10 free-run accuracy f a gr-1244 5.1: r5-1 gr-253 5.4.4.1: r5-117 g.813 5a 11 holdover freq uency stability h st gr-1244 5.2: r5-2 gr-253 5.4.4.2.2: r5- 123, r5-124, r5-125 g.813 10.2a,b 12 holdover entry phase transient h ept gr-1244 5.6: r5-12 gr-253 5.4.4.2.2: r5- 122 g.813 10.2b 13 wander generation w gen gr-1244 5.3: r5-4, r5- 5 gr-253 5.4.4.3.2: r5- 133, r5-134 g.813 7.1 a,b 14 wander transfer w tr gr-1244 5.4: r5-6 gr-253 5.4.4.2.4: r5- 129, r5-130, r5-131 g.813 9.0 a,b 15 jitter generation j g gr-1244 5.5: r5-7 gr-253 5.6.1: r5-235 g.813 7.3a,b 16 phase transient generation (holdover to normal transition) pt g1 gr-1244 5.6: r5-10, o5-11, r5-14 gr-235 5.4.4.3.3: r5- 136, o5-137 17 phase transient generation (alternate reference) pt g2 gr-1244 5.6: r5-10, o5-11, r5-14 gr-235 5.4.4.3.3: r5- 136, o5-137 g.813 10.1 a,b 18 phase transient generation (input transient) pt g3 gr-1244 5.6: r5-10, o5-11, r5-14 gr-235 5.4.4.3.3: r5- 136, o5-137 19 phase transient generation (input interruptions) pt g3 g.813 10.3 a 20 phase changes (during pull-in) p c gr-1244 5.8: r5-17 21 lock time l t 100 s 22 tuning alarm t a -12 +12 ppm note 5 ac electrical characteristics* (continued) parameter symbol min. max. units test conditions
zl30461 data sheet 39 zarlink semiconductor inc. figure 12 - timing parameters measurement voltage levels ac electrical characteristics - timing parameter measurements - cmos voltage levels* characteristics symbol typical units 1 threshold voltage v t 0.5v dd v 2 rise and fall threshold voltage high v hm 0.7v dd v 3 rise and fall threshold voltage low v lm 0.3v dd v timing reference points all signals v hm v t v lm t ir, t or t if, t of
zl30461 data sheet 40 zarlink semiconductor inc. figure 13 - microport timing ac electrical characteristics - microprocessor timing* characteristics symbol min. max. units test conditions 1ds low t dsl 65 ns 2ds high t dsh 100 ns 3cs setup t css 0ns 4ds hold t csh 0ns 5r/w setup t rws 20 ns 6r/w hold t rwh 5ns 7 address setup t ads 10 ns 8 address hold t adh 10 ns 9 data read delay t drd 60 ns c l = 150 pf 10 data read hold t drh 10 ns 11 data write setup t dws 10 ns 12 data write hold t dwh 5ns dsh t dsl t dsw t dhw t drd t drh t valid data valid data adh t ads t rws t css t csh t rwh t t v t v t v t v t v t v __ ds __ cs __ r/w a0 - a4 d0 -d7 read d0 -d7 write
zl30461 data sheet 41 zarlink semiconductor inc. figure 14 - st-bus and gci output timing ac electrical characteristics - st-bus and gci output timing* characteristics symbol min. max. units test conditions 1f16o pulse width low t f16l 56 62 ns 2 f8o to f16o delay t f16d 27 33 ns 3c16o pulse width low t c16l 26 32 ns 4 f8o to c16o delay t c16d -3 3 ns 5 f8o pulse width high t f8h 119 125 ns 6 c8o pulse width low t c8l 56 62 ns 7 f8o to c8o delay t c8d -3 3 ns 8f0o pulse width low t f0l 241 247 ns 9 f8o to f0o delay t f0d 119 125 ns 10 c4o pulse width low t c4l 119 125 ns 11 f8o to c4o delay t c4d -3 3 ns 12 c2o pulse width low t c2l 240 246 ns 13 f8o to c2o delay t c2d -3 3 ns f16l t f16d t c16l t c16d t f8h t c8d t c8l t c4l t c4d t f0l t f0d t c2d t c2l t t v t v t v t v t v t v ____ f16o ____ c16o f8o c8o ___ f0o ___ c4o c2o tc = 125s tc = 61.04ns tc = 125s tc = 122.07ns tc = 244.14ns tc = 125s tc = 488.28ns t v
zl30461 data sheet 42 zarlink semiconductor inc. ac electrical characteristics - ds1, ds2 and c19o clock timing* figure 15 - ds1, ds2 and c19o clock timing ac electrical characteristics - c155o and c19o clock timing* characteristics symbol min. max. units test conditions 1 c6o pulse width low t c6l 75 83 ns 2 f8o to c6o delay t c6d -4 11 ns 3 c1.5o pulse width low t c1.5l 320 328 ns 4 f8o to c1.5o delay t c1.5d -4 11 ns 5 c19o pulse width high t c19h 23 29 ns 6 f8o to c19o delay t c19d -5 7 ns characteristics symbol min. max. units test conditions 1 c155o pulse width low t c155l 2.6 3.8 ns 2 c1550 to c19o rising edge delay t c19dlh -1 7 ns 3 c155o to c19o falling edge delay t c19dhl -2 6 ns t v t v t v t v f8o c6o c1.5o c19o tc = 125s tc = 158.43ns tc = 647.67ns tc = 51.44ns c6l t c6d t c19h t c19d t c1.5h t c1.5d t
zl30461 data sheet 43 zarlink semiconductor inc. figure 16 - c155o and c19o timing ac electrical characteristics - input to output phase alignment (refalign change from 1 to 0)* characteristics symbol min. max. units test conditions 1 8 khz ref pulse width high t r8h 100 ns 2 8 khz to f8o re f input delay t r8d -6 29 ns 3 1.544 mhz ref pulse width high t r1.5h 100 ns 4 1.544 mhz ref input to f8o delay t r1.5d 335 350 ns 5 2.048 mhz ref pulse width high t r2h 100 ns 6 2.048 mhz ref input to f8o delay t r2d 225 272 ns 7 19.44 mhz ref pulse width high t r19h 20 ns 8 19.44 mhz to f8o input delay t r19d 821 ns 9 19.44 mhz ref input to c19o delay t r19c19d 621 ns 10 reference input rise and fall time t ir , t if 10 ns c155p c19o tc = 51.44ns tc = 6.47ns c155l t c19dlh t c19dhl t 1.25v t v note : delay is measured from the rising edge of c155p clock (single ended) at 1.25v voltage level to the rising and falling edges of c19o at v voltage levels t
zl30461 data sheet 44 zarlink semiconductor inc. figure 17 - input reference to output clock phase alignment ac electrical characteristics - input control timing* figure 18 - input control signal setup and hold time characteristics symbol min. max. units test conditions 1 input control setup time t s 100 ns 2 input control hold time t h 100 ns f8o ms1, ms2 rsel t v t v s t h t
zl30461 data sheet 45 zarlink semiconductor inc. ac electrical characteristics - e3 and ds3 output timing* figure 19 - e3 and ds3 output timing 4.2 performance characteristics characteristics symbol min. max. units test conditions 1 c44o clock pulse width high t c44h 11 13 ns 2 c11o clock pulse width high t c11h 526ns 3 c34o clock pulse width high t c34h 13 16 ns 4 c8.5o clock pulse width high t c8.5h 924ns performance characteristics - mode switching* characteristics typical units test conditions 1 core pll holdover accuracy 0.000032 ppm 2 holdover stability 4.6 ppm determined by stability of the on-board tcxo 3 frequency limit range (lock pin and flim bit) 104 ppm relative to osci 4 capture range (truelock bit) 142 ppm relative to osci 5 reference acceptance threshold 12 ppm relative to osci tested without presence of jitter on reference clock lock time 6 6 hz or 12 hz filter 6 s t v t v t v t v c44o c11o c34o c8.5o tc = 22.35ns tc = 89.41ns tc = 29.10ns tc = 116.39ns c44h t c11h t c34h t c8.5h t
zl30461 data sheet 46 zarlink semiconductor inc. note 6: the phase slope is less than 7.5 ppm if the step in phase is less than 120 ns. 7 1.5 hz filter 20 s 8 0.1 hz filter 75 s output phase continuity (mtie) 9 reference switching: pri => sec, sec => pri 50 5 ns ns pri = sec = 8 khz pri or sec = 1.544 mhz, 2.048 mhz, 19.44 mhz 10 switching from normal mo de to holdover mode 0 ns 11 switching from holdover mode to normal mode 50 2 ns ns pri = sec = 8 khz pri or sec = 1.544 mhz, 2.048 mhz, 19.44 mhz (for 0 ppm frequency offset) output phase slope 12 0.1 hz filter 885 ns sec g.813 option 2 gr-253 sonet stratum 3 gr-253 sonet smc 13 1.5 hz filter 41 ns 1.326ms g.813 option 1, gr-1244 stratum 3, note 6 14 6 hz filter 50 ns sec g.813 option 1, note 6 15 12 hz filter 1200 s sec performance characteristics - mode switching* (continued) characteristics typical units test conditions
zl30461 data sheet 47 zarlink semiconductor inc. * supply voltage and operating temperature ar e as per recommended operating conditions. performance characteristics: measured output jitter - gr-253-core and t1.105.03 conformance* telcordia gr-253-core and ansi t1.105.03 jitter generation requirements zl30461 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c155o clock output 1oc-3 155.52 mbps 65 khz to 1.3 mhz 0.15 ui pp 0.964 0.425 ns p-p 0.048 ns rms 2 12khz to1.3mhz (category ii) 0.1 ui pp 0.643 0.508 ns p-p 0.01 ui rms 0.064 0.048 ns rms 3 500 hz to 1.3 mhz 1.5 ui pp 9.645 0.548 ns p-p 0.063 ns rms ja77p/n clock output 4oc-12 622.08 mbps 12 khz to 5 mhz (category ii) 0.1 ui pp 161 34.9 ps p-p 2.8 ps rms ja19mo clock output 5oc-12 622.08 mbps 12 khz to 5 mhz (category ii) 0.1 ui pp 161 91.68 ps p-p 7.06 ps rms c19o clock output 6oc-3 155.52 mbps 65 khz to 1.3 mhz 0.15 ui pp 0.964 0.886 ns p-p 0.146 ns rms 7 12khz to1.3mhz (category ii) 0.1 ui pp 0.643 0.909 ns p-p 0.01 ui rms 0.064 0.149 ns rms 8 500 hz to 1.3 mhz 1.5 ui pp 9.645 0.973 ns p-p 0.151 ns rms
zl30461 data sheet 48 zarlink semiconductor inc. performance characteristics: measured output jitter - t1.403 conformance* * supply voltage and operating temperature ar e as per recommended operating conditions. performance characteristics: measured output jitter - g.747 conformance* * supply voltage and operating temperature ar e as per recommended operating conditions. performance characteristics: measured output jitter - t1.404 conformance* * supply voltage and operating temperature ar e as per recommended operating conditions. ansi t1.403 jitter generation requirements zl30461 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c1.5o clock output 1ds1 1.544 mbps 8 khz to 40 khz 0.07 ui pp 45.3 0.922 ns p-p 2 10 hz to 40 khz 0.5 ui pp 324 1.45 ns p-p itu-t g.747 jitter generation requirements zl30461 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c6o clock output 1 6312 kbps (ds2) 10 hz to 60 khz 0.05 ui pp 7.92 1.96 ns p-p ansi t1.404 jitter generation requirements zl30461 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c44o clock output 1ds3 44.736 mbps 30 khz to 400khz 0.05 ui pp 1.12 0.892 ns p-p 2 10 hz to 400 khz 0.5 ui pp 11.2 1.5 ns p-p
zl30461 data sheet 49 zarlink semiconductor inc. performance characteristics: measured output jitter - g.732, g.735 to g.739 conformance* * supply voltage and operating temperature ar e as per recommended operating conditions. performance characteristics: measured output jitter - g.751 conformance* * supply voltage and operating temperature ar e as per recommended operating conditions. itu-t g.732, g.735, g.736, g.737, g.738, g739 jitter generation requirements zl30461 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c16o , c8, c4 and c2 clock outputs 1e1 2048 kbits/s 20 hz to 100 khz 0.05 ui pp 24.4 1.26 ns p-p itu-t g.751 jitter generation requirements zl30461 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c34 clock outputs 1e3 34368 kbits/s 100 hz to 800 khz 0.05 ui pp 1.45 1.04 ns p-p
zl30461 data sheet 50 zarlink semiconductor inc. performance characteristics: measured output jitter - g.813 conformance - option 1 * supply voltage and operating temperature ar e as per recommended operating conditions. itu-t g.813 jitter generation requirements zl30461 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c155o clock output 1stm-1 155.52 mbps 65 khz to 1.3 mhz 0.1 ui pp 0.643 0.425 ns p-p 0.048 ns rms 2 500 hz to 1.3 mhz 0.5 ui pp 3.215 0.548 ns p-p 0.063 ns rms ja77p/n clock output 3stm-4 622.08 mbps 250 khz to 5mhz 0.1 ui pp 161 20.32 ps p-p 1.516 ps rms 4 5 khz to 20 mhz 0.5 ui pp 804 86.36 ps p-p 6.8 ps rms ja19mo clock output 5stm-4 622.08 mbps 250 khz to 5mhz 0.1 ui pp 161 81.5 ps p-p 6.7 ps rms 6 5 khz to 20 mhz 0.5 ui pp 804 177.8 ps p-p 14 ps rms c19o clock output 7stm-1 155.52 mbps 65 khz to 1.3 mhz 0.1 ui pp 0.643 0.866 ns p-p 0.146 ns rms 8 500 hz to 1.3 mhz 0.5 ui pp 3.215 0.973 ns p-p 0.151 ns rms c16o , c8o, c4o and c2o clock output 9e1 2048 kbps 20 hz to 100 khz 0.05 ui pp 24.4 1.26 ns p-p
zl30461 data sheet 51 zarlink semiconductor inc. performance characteristics: measured output jitter - g.813 conformance - option 2 itu-t g.813 jitter generation requirements zl30461 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c155o clock output 1 stm-1 155.52 mbps 12 khz to 1.3 mhz 0.1 ui pp 0.643 0.508 ns p-p 0.058 ns rms ja77p/n clock output 2 stm-4 622.08 mbps 12 khz to 5mhz 0.1 ui pp 161 34.9 ps p-p 2.8 ps rms ja19mo clock output 3 stm-4 622.08 mbps 12 khz to 5mhz 0.1 ui pp 161 91.68 ps p-p 7.06 ps rms c19o clock output 4 stm-1 155.52 mbps 12 khz to 1.3 mhz 0.1 ui pp 0.643 0.500 ns p-p 0.071 ns rms
previous package codes package code acn date issue apprd. c zarlink semiconductor 2003 all rights reserved. 1 dimension
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